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technical data cmos timer with ram and i 2 c-bus control . INA8583N t a = -20 t 70 c INA8583N i s a t i m er wi t h r a m and i 2 c - bus cont rol . desi gned for use i n ap- pl i a nces havi ng i 2 c-bus as clock/calendar/tim er/a larm /events counter for turn- i ng on funct i ons of t h e appl i a nce at preset t i m e or upon com p l e t i on of an event . to be used i n audi o and appl i a nces. features: - i 2 c- bus interface operating supply voltage: 2.5 v to 6 v; - c l ock operat i ng suppl y vol t a ge ( 0 70 ): 1.0 v t o 6 v; - operating current (at f scl = 0hz): 50 ; - c l ock funct i on wi t h four y ear cal endar; - 24 or 12 hour form at ; - 32.768 khz or 50hz t i m e base; - serial bus (i 2 c); - au to m a tic wo rd ad d r ess in crem en tatio n ; - program m a bl e al arm , t i m er and i n t e rrupt funct i o n ; - operat i ng t e m p erat ure range: -20 t o +70 . - table1 ? pin assignment p i n osci osco a0 gnd sda scl int vcc 1 2 3 4 5 6 7 8 generat o r i nput , 50hz or occurrences generat o r out put address i nput gnd data for i 2 c - bus c l ock pul ses for i 2 c - bus open-drai n i n t e rrupt out put suppl y vol t a ge pinning diagram osci 1 8 vcc osco 2 7 int a0 3 6 scl gnd 4 5 sda fig.1 1
ina8583 block diagram INA8583N INA8583N osci 100hz 00 o s c o 0 1 int v cc gnd 0 7 0 8 a 0 0 f s c l f f sda ina8583 oscillat o r 32.768khz divider 1:256 or 100:128 control logic power-on reset i 2 c-bus interface address register control/status hundredth of a second seconds minutes hours year/date weekday/months timer alarm control alarm regisers or ram ram (240 8) fig. 2. 2
ina8583 table 2 ? recom m e nd-operating conditions param e t e r l i m i t s n o t e sym b o l unit not m o re not less supply voltage, vcc, v ? operating ? clock 2.5 1.0 6.0 6.0 t am b =0 +70 c low input voltage, vil, v 0 0.3*vcc high input voltage, vih, v 0.7*vcc vcc operating am bient tem - perature, tam b, c - 2 0 + 7 0 input frequency, f i , mhz 1 only for event m ode table3 ? a b s o l u t e ma x i mu m r a t i n g param e t e r l i m i t s n o t e sym b o l unit not m o re not less supply voltage, vcc, v -0.8 7,0 input voltage for all inputs, v i , v -0.8 vcc+0.8 note1 max output current, io, m a 10 max input current, i i , m a 10 current through inputs 04 or 08, i dd , i ss , m : 5 0 power dissipation on package, j tot , mw 3 0 0 power dissipation on output , j h , m w 50 storage tem p erature, tstg, - 6 5 + 1 5 0 notes: 1. if voltage on diode is higher than v cc or lower than gnd, the current will flow, the cur- rent should be not m o re than 0.5m a. 3
ina8583 table 4 ? electrical param e ters. param e ter, sym bol lim it testing con- ditions tem p era- ture, c unit not less not m o re supply supply current ,i , a 200 vcc=6v f scl = 100khz t=-20 +25 +70 supply current for clock, i 0 , 50 vcc=5v a 10 vcc=1v data storage supply cur- rent, i ccr , a 5 note 1 v cc = 1v 2 v cc = 1v i 2 c -bus enable level, v por , v 1.5 2.3 note 2 input/output sda low output current, i ol , ma 3 vcc= 6 v vol= 0.4 v input leakage current, | i i | , a 1 vcc= 6 v v il = 0 v v ih = 6 v scl, sda input capacity, i ,pf 7 v i =0 v inputs a0, osci input leakage current, | i i | , na 250 vcc= 6 v v il = 0 v v ih = 6 v output int output low current, i ol , ma 3 vcc=6.0 v v ol =0,4 v input leakage current, | i i | , a 1 vcc= 6 v v il = 0 v v ih = 6 v notes: 1. for event m ode or 50hz onl y . 2. the i 2 c - bus l ogi c i s di sabl ed i f v cc < v por . 4
ina8583 INA8583N contains 256 8 ram 8-bit. the word address register which is increm ented autom a ti- cally, built-in 32.768 khz oscillator circuit, frequenc y divider, interface of two line bi-directional serial i 2 c-bus and power-on reset circuit. the first 8 bits of the ram (addresses 00 07) are designated ass addressable 8-bit parallel registers. the first register (address 00) is used as a control/status register. the m e m o ry addresses 01 to 07 are used as counters for the clock function. the m e m o ry address 08 0f m a y be used as free ram locations or m a y be program m e d as alarm registers. the following m odes can be selected by setting the control/status register: ? clock m ode from 32.768 khz; ? clock m ode from 50 hz; ? event counter m ode. in the clock m ode hundredths of a second, s econds, m i nutes, hours, date, m onth (four-year calendar) and a weekday are stored in a bcd form at . the tim er register st ores up to 99 days. the event counter m ode is used for counting pulses applied to the oscillator input (osco left open- circuit). in bcd form at the event counter stores up to 6 digits. by setting the alarm enabling bit of the control/s tatus register the alarm control register (ad- dress 08) is activated. by setting the alarm control register the following m a y be program m e d: ? dated alarm ; ? w eekday alarm ; ? daily alarm ; ? tim e r alarm . in the clock m ode the tim er register (address 07) m a y be program m e d to count hundredths of a second, seconds, m i nutes, hours or days. days are counted when an alarm is not program m e d. w h enever an alarm event occurs the alarm flag of the control/status register is set, and an overf low condition of the tim er will set the tim er f l ag. the open drain interrupt output is switched on (active low ) when the alarm or tim er f l ag is set. the f l ags rem a in set until directly reset by a write operation to register (00 address). w h en the alarm is disabled the rem a ining alarm registers (addresses 09 0f) m a y be used as free ram. in the clock m odes 24hr or 12hr form at can be selected by setting the m o st significant bit of the hours counter register. 5
ina8583 register arrangement. c o n t r o l / s t a t u s c o n t r o l / s t a t u s 0 0 hundredth of second d1 d0 01 s e c o n d s d 3 d 2 0 2 m i n u t e s d 5 d 4 0 3 h o u r s f r e e 0 4 y e a r / d a t e f r e e 0 5 w eekday/m o n t h f r e e 0 6 tim e r tim e r 1 t i m e r 0 0 7 alarm control alarm control 08 hundredth of second alarm d1 alarm d0 09 alarm seconds d3 d2 0a alarm m i nutes d5 d4 0b alarm hours free 0c alarm date free 0d alarm m onth free 0e alarm tim er alarm tim er 0f free ram f r e e r a m clock m odes event counter fig. 3 . table 5. ? cycle length of the tim e counters, clock m odes. unit counting cycle carry to next unit contents of the m onth counter hundredths of a sec- ond 00 99 99 to 00 seconds 00 59 59 to 00 minutes 00 59 59 to 00 hours (24 h) 00 23 23 to 00 hours (12 h) 12 ? , 01 ? 11 ? , 12 , 01 11 11 to 12 ? date 01 31 01 30 01 29 01 28 31 to 01 30 to 01 29 to 01 28 to 01 1, 3, 5, 7, 8, 10, 12 4, 6, 9, 11 2, year = 0 2, year = 1, 2, 3 months 01 21 12 to 01 year 0 3 3 to 0 w eekdays 0 6 6 to 0 tim e r 00 99 no carry 6
ina8583 the year and date are packed into m e m o ry location 05. the weekdays and m onths are packed into m e m o ry location 06. w h en reading thes e m e m o ry locations the year and weekdays m a y be m a sked out when the m a sk flag of the control/statu s register is set. this allows the user to read the date and m onth counters only. in the event counter m ode data are stored in bcd form at. d5 is the m o st significant and do the least significant digit. in this m ode the internal divider is by-passed. by setting the alarm enable bit of the control/status register the alarm control register (address 08) is activated. all f unctions of the alarm , tim er a nd interrupt output are controlled by the contents of the alarm control register. all alarm registers are arranged starting from 08 address. an alarm signal is generated when the contents of the alarm registers m a tches bit-by-bit the contents of the involved counter registers. the year and weekday bits are ignored in a dated alarm . a daily alarm ignored the m onth and date bits. w h en a weekday alarm is selected, for com p arison a bit will be selected from the alarm register per the weekday (address oe) corresponding to the weekday on which the alarm is activated. interrupt output (with open drain) is program m e d by setting the alarm control register. it en- ables (active low ) when the alarm flag or tim er fl ag are set. the voltage level in on state (high) on the interrupt output m a y be m o re than the supply voltage. a 32.768 khz quartz crystal m a y be connected to osci (pin 1) and osco (pin 2). a trim - m e r capacitor between osci and supply is used fo r tuning the oscillator. a 100 hz clock signal is derived from the quartz oscillator for the clock counters. in the 50hz clock m ode or event-counter m ode the oscillator is disabled and the oscillator input is switched to a high im pedance state. this allows the user to feed the 50hz reference fre- quency or an external high speed event signal into the input osci. w h en power-up occurs the i 2 c-bus interface, the control/status register and all clock count- ers are reset. after the device starts tim e-keep ing in the 32.768khz clock m ode with the 24hr for- m a t on the square wave appears at the interrupt output pin (starts high). this m a y be abolished by setting the alarm enable bit in the control/status register. the 2 nd signal of interface of i 2 c-bus is generated as soon as the supply voltage below the reset level of i 2 c-bus interface. this reset signal does not affect the registers of hour counter and control/status register. it the recom m e nded to set the stop counting flag of the control/status register bef o re loading the actual tim e into the counters. loading of illegal states m a y lead to a tem porary clock m a lfunc- tion. i 2 c-bus is a bi-directional, two-line com m unica tion between different ics and m odules. the two lines are a serial data line (sda) and a serial clock line (scl). both lines shall be connected to a positive supply via a resistor since in ic these outputs have ?open drain?. data transfer m a y be initiated only when the bus is not busy. 7
ina8583 one data bit is transferred during each clock pulse . the data on the sda line m u st rem a in stable during the high period of the clock pulse as changes in the data line at this tim e will be interpreted as a control signal. . bit transfer sda scl data change valid of data a l l o w e d fig. 4. both sda and scl lines rem a in high when the bus is not busy. the high-to-low tran- sition of the data line, while the clock is high is defined as the start c ondition (s). a low - to-high transition of the data line while the clock is high is defined as the stop condition ( ). definition of start and stop conditions. sda scl s p fig. 5. a device generating a m e ssage is a ?transm itter? a device receiving a m e ssage is a ?re- ceiver?. the device that controls the m e ssage is the ?m aster?, and the devices which are controlled by the m a ster are ?slaves?. the num ber of data bytes transferred between the start and stop conditions from the trans- m itter to receiver is unlim ited. each byte of eight bits is followed by an acknowledge bit. 8
ina8583 acknow ledgment on the i 2 -bus. c l o c k p u l s e f o r start condition acknowledgem e nt scl from m a ster 1 2 8 9 data output by receiver data output by transm itter s fig. 6. the acknowledge bit is a high level signal put on the bus by the transm itter during which tim e the m a ster generates an extra acknowledge re lated clock pulse. a slave receiver which is ad- dressed m u st generate an acknowledge after the recep tion of each byte. also a m a ster receiver m u st generate an acknowledge after the reception o each byte that has been clocked out of the slave transm itter. the device that acknowledges m u st pull down the sda line during the acknowledge clock pulse. a m a ster receiver m u st signa l an end of date to the transm itter by not generating an acknowledge on the last byte that has been clocked out of the slave. in this event the transm itter m u st leave the data line high to enable the m a ster to generate a stop condition. bef o re any date is transm itted on the i 2 c-bus, the device which should respond is addressed f i rst. the addressing is always carried out with the f i rst byte transm itted af ter the start procedure. master transmits to slave receiver (write) mode. acknowledgem e nt acknowledgem e nt acknowledgem e nt from slave from slave from slave s slave address 0 w o rd address data r/w n bytes a u t o i n c r e m e n t m e m o r y w o r d a d d r e s s fig. 7. 9
ina8583 master reads after setting w o rd address (w rite w o rd address; read data). acknowledgem e nt acknowledgem e nt acknowledgem e nt from slave from slave from slave s slave address 0 w o rd a d d r e s s s s lave address 1 r / w r / w at this m o m e nt m a ster-transm itter becom e s m a ster-receiver and INA8583N slave-receiver becom e s slave-transm itter. acknowledgem e nt no acknowledgem e nt from m a ster from m a ster data d a t a 1 n byte last byte auto increm ent auto increm ent word address word address fig. 8. master reads slave immediately after first byte (read mode). acknowledgem e nt acknowledgem e nt no acknowledgem e nt from slave from m a ster from m a ster s slave address 1 d a t a data 1 r/w n bytes last byte auto increm ent auto increm ent w o r d a d d r e s s w o r d a d d r e s s fig. 9. 10
ina8583 application circuit v cc v cc v c c v cc r r v cc 0 scl osci INA8583N sda osco gnd v cc 0 scl osci INA8583N sda osco gnd master sda transm itter scl fig.10 11
ina8583 table 6 ? symbols sym b o l d e s c r i p t i o n s s t a r t c o n d i t i o n p s t o p c o n d i t i o n a b i t a c k n o w l e d g e INA8583N address 1 0 1 0 0 0 0 r / w group1 group 2 fig. 11. n s u f f i x p l a s t i c di p ( m s ? 00 1b a ) sy m b o l m i n m a x a 8. 51 10. 16 b 6. 1 7 . 1 1 c 5. 33 d 0. 36 0. 56 f 1. 14 1. 78 g h j 0 10 k 2. 92 3. 81 no t e s : l 7. 62 8. 26 1. d i m e n s i o n s ?a ?, ?b ? d o n o t i n cl u d e m o l d f l as h o r p r o t r u s i o n s . m 0. 2 0 . 3 6 m a x i m u m m o l d f l a s h o r p r o t r u s i o n s 0. 25 m m ( 0 . 010) p e r s i d e . n 0. 38 d i m e ns i o n, m m 2. 54 7. 62 l h m j a b f g d se a t i n g pl a n e n k 0 . 2 5 ( 0 .01 0 ) m t -t - c 1 8 4 5 12

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